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XC9572XL 芯片破解

来源:芯片解密-龙芯世纪   时间:2010-06-17   阅读:1022

XC9572XL 芯片解密是龙芯世纪在 研究中成功破解的典型芯片型号,针对该芯片,我们解密周 期短、价格低、可靠性强。这里,我们将针对XC9572XL芯片的主要技术特征做简单介绍,这里我们仅提供对XC9572XL芯片的主要 功能特征介绍,供客户及各类芯片解密工程师与电子工程师参考借鉴,有芯片解密,ic解密 需求者请直接与我们联系咨询。
 
下面是关于XC9572XL芯片的主要性能特征介绍,我们提供给广大客户及其他各类技术工程师参考借鉴。
• 5 ns pin-to-pin logic delays
• System frequency up to 178 MHz
• 72 macrocells with 1,600 usable gates
• Available in small footprint packages
- 44-pin PLCC (34 user I/O pins)
- 44-pin VQFP (34 user I/O pins)
- 48-pin CSP (38 user I/O pins)
- 64-pin VQFP (52 user I/O pins)
- 100-pin TQFP (72 user I/O pins)
- Pb-free available for all packages
• Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
• Pin-compatible with 5V-core XC9572 device in the
44-pin PLCC package and the 100-pin TQFP package
WARNING: Programming temperature range of
TA = 0° C to +70° C
 
XILINUX XC9572XL Description:
The XC9572XL is a 3.3V CPLD targeted for high-performance,
low-voltage applications in leading-edge communications and computing systems. It is comprised of four
54V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 5 ns.
 
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