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EPC1441芯片解密

来源:芯片解密-龙芯世纪   时间:2010-07-07   阅读:2221

EPC1441 芯片解密是龙芯世纪在 研究中成功破解的典型芯片型号,针对该芯片,我们解密周 期短、价格低、可靠性强。这里,我们将针对EPC1441芯片的主要技术特征做简单介绍,这里我们仅提供对EPC1441芯片的主要 功能特征介绍,供客户及各类芯片解密工程师与电子工程师参考借鉴,有芯片解密,ic解密 需求者请直接与我们联系咨询。

下面是关于EPC1441芯片的主要性能特征介绍,我们提供给广大客户及其他各类技术工程师参考借鉴。

EPC1441 Features
Serial device family for configuring ACEXTM, APEXTM (including
APEX 20K, APEX 20KC, and APEX 20KE), FLEX? (FLEX 10KE and
FLEX 10KA), and MercuryTM devices
Easy-to-use 4-pin interface to ACEX, APEX, FLEX, and Mercury
devices
Low current during configuration and near-zero standby current
5.0-V and 3.3-V operation
Software design support with the Altera? QuartusTM and
MAX+PLUS? II development systems for Windows-based PCs as
well as Sun SPARCstation, and HP 9000 Series 700/800
Programming support with Altera’s Master Programming Unit
(MPU) and programming hardware from Data I/O,
BP Microsystems, and other manufacturers
Available in compact plastic packages (see Figures 1 and 2)
- 8-pin plastic dual in-line package (PDIP)
- 20-pin plastic J-lead chip carrier (PLCC) package
- 32-pin plastic thin quad flat pack (TQFP) package
EPC2 device has reprogrammable Flash configuration memory
- 5.0-V and 3.3-V in-system programmability (ISP) through the
built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG)
interface
- Built-in JTAG boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
- ISP circuitry is compatible with IEEE Std. 1532 for EPC2
configuration device
- Supports programming through Serial Vector Format Files
(.svf), JamTM Standard Test and Programming Language
(STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), and the
MAX+PLUS II software via the MasterBlasterTM,
ByteBlasterMVTM, or BitBlasterTM download cable
- nINIT_CONF pin allows a JTAG instruction to initiate APEX,
FLEX, or Mercury device configuration
- Can be programmed with Programmer Object Files (.pof) for
EPC1 and EPC1441 devices


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