来源：芯片解密-龙芯世纪 时间：2010-07-07 阅读：1189次
complete family of CMOS EPLDs solves design tasks ranging from fast 20-pin address decoders to 100-pin LSI custom peripherals.
the advanced MAX5000 architecture combines the speed,ease of use,and familiarity of PAL devices with the density of programmable gate arrays.
MAX 5000 EPLDs provide 15-ns combinatorial delays,counter frequencies up 100 MHz,pipelined data rates of 100 MHz.
Available in a wide variety of packages, including DIP,SOIC,J-lead,FGA,and QFP formats in windowed ceramic and plastic one-time-programmable versions.
MAX+PLUS and MAX+PLUS Ⅱ PC-and workstation-based development tools compile large designs in minutes.
an industry-standard EDLF interface to workstation and third-party CAE tools is available.