来源：芯片解密-龙芯世纪 时间：2010-09-30 阅读：2825次
The W925E/C240 is an all in one single 8-bit micro-controller with widely used Calling Identity Delivery (CID) function. The 8-bit CPU core is based on the 8051 family; therefore, all the instructions are compatible to the Turbo 8051 series. The CID part consisted of FSK decoder, DTMF receiver, CPE* Alert Signal (CAS) detector and Ring detector. Also built-in DTMF generator and FSK generator with baud rate 1200 bps (bits/sec). Using W925E/C240 can easily implement the CID adjunct box and the feature phone or Short Message Service (SMS) phone with CID function. The main features are listed in the next section.
APPLICATION: The SMS phone with CID function and CID adjunct box.
CPU: 8-bit micro-controller is similar to the 8051 family.
EEPROM type(E version) operating voltage:
MCU: Depend on the operating vol. option. Either 2.4 to 3.6V or 3.0 to 5.5V for operating. If 2.4 to 3.6V be selected, the MCU operating range is from 2.4 to 3.6V, else if 3.0 to 5.5V be selected, the MCU operating range is from 3.0 to 5.5V. CID: 3.0 to 5.5V.
MASK type(C version) operating voltage:
MCU: 2.2 to 5.5V.
CID: 3.0 to 5.5V.
Main oscillator: 3.58MHz crystal for CID and DTMF function. And built-in RC oscillator.
Sub oscillator: 32768Hz crystal.
Main and sub oscillators are enable/disable by bit control individually.
ROM: 256K bytes internal flash EEPROM/MASK ROM type.
Up 128K bytes for program ROM.
Total 256K bytes for look-up table ROM.
Separate 256K into 4 pages, each page is 64K addressable.
256 bytes on chip scratch-pad RAM.
8K bytes on chip RAM for MOVX instruction.
Compatible with Bellcore TR-NWT-000030 & SR-TSV-002476, British Telecom(BT) SIN227, U.K. Cable Communication Association(CCA) specification.
FSK modulator/demodulator: for Bell 202 and ITU-T V.23 FSK with 1200-baud rate.
CAS detector: for dual tones of Bellcore CAS and BT Idle State and Loop State Dual Tone Alert Signal (DTAS).
Ring detector: for line reversal for BT, ring burst for CCA or ring signal for Bellcore.
Two independent OP amps with adjustable gain for Tip/Ring and Telephone Hybrid connections.
I/O: 40 I/O pins.
P0: Bit and byte addressable. I/O mode can be bit controlled. Open drain type.
P1~P3: Bit and byte addressable. Pull high and I/O mode can be bit controlled.
P4: Byte addressable. Pull high and I/O mode can be bit controlled.
Note: ”CPE*” Customer Premises Equipment
Dual-clock slow operation mode: System is operated by the sub-oscillator (Fosc=Fs and Fm is stopped)
Idle mode: CPU hold. The clock to the CPU is halted, but the interrupt, timer and watchdog timer block work normally but CID function is disabled.
Power down mode: All activity is completely stopped and power consumption is A.?less than 1
Timer: 2 13/16-bit timers, or 8-bit auto-reload timers, that are Timer0 and Timer1.
Watchdog timer: WDT can be programmed by the user to serve as a system monitor.
Interrupt: 11 interrupt sources with two levels of priority.
4 interrupts from INT0, INT1, INT2 and INT3.
2 interrupts from Timer0, Timer1.
1 interrupt from Serial port.
1 interrupt from CID.
1 interrupt from 13/14-bit Divider.
1 interrupt from Comparator.
1 interrupt from Watch Dog Timer.
Divider: 13/14 bit divider, clock source from sub-oscillator, therefore, DIVF set every 0.25/0.5 second.
Comparator: 1 analog inputs from VNEG pin, 2 reference input pins, one is from VPOS pin and another is from internal regulator output.
An 8-bit serial transceiver with SCLK and SDATA.